The present disclosure relates to integrated circuit (IC) structures, and more specifically, to IC structures having vias in post zero via layers positioned outside of a keep out zone over a TSV to reduce stresses caused by pumping.
In integrated circuit (IC) structures, through silicon vias (TSVs) are relatively large vertically extending contacts used to electrically couple substrates that include circuitry. Each TSV extends through the respective substrate and couples to back-end-of-line (BEOL) interconnects such as vias and metal wires. BEOL refers to IC structure fabrication steps performed on the semiconductor wafer in the course of device manufacturing following first metallization. TSVs allow three-dimensional stacking of advanced ICs. TSVs use copper surrounded by a refractory metal liner to prevent diffusion of the copper into surrounding materials. TSVs may extend through dielectric material and semiconductor material, the latter of which may include active devices such as transistors.
As current semiconductor technology nodes reach wiring sizes of less than 10 nanometers, one challenge related to TSVs is referred to as ‘pumping’. Pumping is a phenomenon in which end surfaces of TSVs deform due to stresses created by the large differences in coefficient of thermal expansion (CTEs) between the copper and the surrounding semiconductor materials. That is, the CTE differences cause stress build up in the TSV and surrounding materials, and cause ends of the TSV to deform, for example, by becoming domed shape. The deformation is transferred through a zero via (V0) interconnect layer that directly contacts the TSV and a first metal layer thereover to other interconnect layers positioned over the TSV. Interconnects within a periphery of the TSV in the later interconnect layers, such as regular copper vias in a first via layer V1 above first metal layer M1, second metal layer M2, etc., are impacted by the pumping as is the lifespan of dielectric layers thereabout. Zero vias (V0) placed over a center of the TSV are known to experience the greatest amount of stress with or without copper pumping and are more susceptible to stress induced voiding (SIV). The TSV deformation can also cause dishing in a first metal layer dielectric due to the raised area requiring additional planarization. The pumping issue is magnified as technology advances to ever smaller and more sensitive wiring sizes.
Approaches to control the pumping include creating smaller TSVs with lower copper volume, annealing the copper prior to planarization to relieve the stress and diminish any deformation, or control the copper microstructure in the TSV. Unfortunately, not all of these approaches are always controllable during semiconductor fabrication. For example, TSV size/volume or when an anneal is performed cannot be altered without departing from a particular IC design specification. In addition, annealing is not always effective. Another approach to improve SIV reliability has been to offset the zero vias (V0) that are in contact with an upper surface of the TSV with respect the TSV center.